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-rw-r--r--arch/arm64/lib/gic.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm64/lib/gic.c b/arch/arm64/lib/gic.c
index 11bb9cd..647e987 100644
--- a/arch/arm64/lib/gic.c
+++ b/arch/arm64/lib/gic.c
@@ -27,7 +27,6 @@
/* distributor registers, offsets from the GICD base */
#define GICD_CTLR 0x000
#define GICD_TYPER 0x004
-#define GICD_IGROUPR(n) (0x080 + (n) * 4)
#define GICD_ISENABLER(n) (0x100 + (n) * 4)
#define GICD_ICENABLER(n) (0x180 + (n) * 4)
#define GICD_ICPENDR(n) (0x280 + (n) * 4)
@@ -79,13 +78,14 @@ int tb_gic_init(uintptr_t gicd, uintptr_t gicc)
lines = gicd_irq_lines(gicd);
/*
- * every interrupt in group 1, the non-secure group. the
- * kernel does not see group 0 interrupts on non-secure
- * hardware, and a bootloader that leaves any line in the
- * secure group strands it.
+ * the group routing is deliberately untouched. the group
+ * registers are the secure world's, a non-secure loader's
+ * writes are dropped on hardware that implements the
+ * security extension, and on emulators that accept them
+ * the timer's per cpu interrupts stop reaching the
+ * kernel. group config belongs to the EL3 monitor, this
+ * loader runs without one.
*/
- for (n = 0; n < lines; n++)
- writel(0xffffffff, REG32(gicd + GICD_IGROUPR(n)));
/* no per interrupt enables, nothing pending */
for (n = 0; n < lines; n++) {