From 00fc82f17cff9295387d516384ecdc443acb1b22 Mon Sep 17 00:00:00 2001 From: Bradley Morgan Date: Sat, 3 Oct 2026 18:57:38 +0000 Subject: tashaboot: arm64 bringup, semihosting payload loader consoles on the pl011 the dtb points at, walks the memory node and chosen, loads an arm64 kernel Image over semihosting and jumps to it with the documented register state. string functions, printf and libfdt are vendored from lk (lk2nd) and u-boot so the libc surface is the one those projects already proved. built and booted on qemu virt, payload exits clean through semihosting. --- include/drivers/serial/pl011.h | 51 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 include/drivers/serial/pl011.h (limited to 'include/drivers/serial/pl011.h') diff --git a/include/drivers/serial/pl011.h b/include/drivers/serial/pl011.h new file mode 100644 index 0000000..71ffc5a --- /dev/null +++ b/include/drivers/serial/pl011.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * pl011.h - PL010/PL011 register defs, shared struct like u-boot + * + * Copyright (C) 2026 Bradley Morgan + */ + +#ifndef _DRIVERS_SERIAL_PL011_H +#define _DRIVERS_SERIAL_PL011_H + +#include +#include + +/* + * the PL010 and PL011 overlap in the common registers so one struct + * covers both, same trick as u-boot's serial_pl01x.c + */ +struct pl01x_regs { + uint32 dr; /* 0x00 Data register */ + uint32 ecr; /* 0x04 Error clear register (Write) */ + uint32 pl010_lcrh; /* 0x08 Line control, high byte */ + uint32 pl010_lcrm; /* 0x0C Line control, middle byte */ + uint32 pl010_lcrl; /* 0x10 Line control, low byte */ + uint32 pl010_cr; /* 0x14 Control register */ + uint32 fr; /* 0x18 Flag register (Read only) */ + uint32 reserved; /* 0x1C */ + uint32 ilpr; /* 0x20 IrDA low-power counter */ + uint32 pl011_ibrd; /* 0x24 Integer baud rate divisor */ + uint32 pl011_fbrd; /* 0x28 Fractional baud rate divisor */ + uint32 pl011_lcrh; /* 0x2C Line control register */ + uint32 pl011_cr; /* 0x30 Control register */ + uint32 pl011_ifls; /* 0x34 Interrupt FIFO level select */ + uint32 pl011_imsc; /* 0x38 Interrupt mask set/clear */ + uint32 pl011_ris; /* 0x3C Raw interrupt status */ + uint32 pl011_mis; /* 0x40 Masked interrupt status */ + uint32 pl011_icr; /* 0x44 Interrupt clear register */ +}; + +#define UART_PL01x_FR_TXFE 0x80 +#define UART_PL01x_FR_RXFF 0x40 +#define UART_PL01x_FR_TXFF 0x20 +#define UART_PL01x_FR_RXFE 0x10 +#define UART_PL01x_FR_BUSY 0x08 +#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY) + +/* drivers/serial/pl011.c */ +void pl011_init(uintptr_t base, uint32 clock, uint32 baud); +void pl011_putc(uintptr_t base, char c); +int pl011_getc(uintptr_t base); + +#endif -- cgit v1.2.3