tashaboot: smp, psci, initrd, timer, cache by va

The bootloader now does the whole job of machine firmware it owns:
boots 4 cpus, hands over an initrd, answers PSCI, and carries the
delay and cache primitives the arch layer needs.

SMP: the secondary pen is the Wait For Event mechanism from the
manual (B2-144, D1-2255), each secondary watches its spin gate,
WFE, the release writes the entry and SEVs, the recheck after each
wake covers a release that lands between the load and the sleep.
The gates land in the dtb cpu-release-addr slots, rewritten in
place by a small walker, no libfdt, structure per the devicetree
specification, values only, the properties themselves are fixed at
build time like firmware shipping a fixed blob.

PSCI 0.2 at EL2 (DEN 0022): the HVC trap arrives at the current EL
SP_ELx sync slot (EC 0x16 in ESR_EL2, the vector layout Table D1-7),
dispatch on the standard function ids, VERSION, CPU_ON writes the
target gate and SEVs, CPU_OFF clears the gate and returns to the
pen, SYSTEM_OFF and SYSTEM_RESET drive RMR_EL2.RR. On qemu the cores
are held by the machine's own firmware and released through its PSCI
(hvc with -kernel, smc with virtualization=on), the handler here is
the real hardware path where the bootloader is the conduit.

The initrd handoff: loaded at a fixed address clear of the image
and dtb, the dtb /chosen carries linux,initrd-start and -end.

Delays are the generic timer (D10), CNTFRQ_EL0 frequency, CNTVCT_EL0
count, busy wait, no interrupts. Cache maintenance by virtual
address, dc cvac, dc ivac, dc civac, ic ivau with the barrier pairs
the manual requires, the by VA form beats set and way when the
range is known.

Boot receipt, 4 cpus, el2, initrd:

  tashaboot 0.1
  initrd at 46000000
  [    0.000000] Booting Linux on physical CPU 0x0000000000
  [    0.130621] smp: Brought up 1 node, 4 CPUs
  [    1.830692] Run /init as init process
  tashaboot linux userspace reached
  cores: 4
  BusyBox v1.37.0 built-in shell (ash)
  ~ #

Signed-off-by: Bradley Morgan <brads@mainlining.org>

1 files changed, 46 insertions, 0 deletions

diff --git a/common/main.c b/common/main.c
index 8d5ee63..0786027 100644
--- a/common/main.c
+++ b/common/main.c
@@ -37,6 +37,8 @@
 #include <boot.h>
 
 #define TB_VERSION "0.1"
+#define TB_INITRD_ADDR	0x46000000ULL
+#define TB_INITRD_FILE	"initrd.cpio.gz"
 
 extern int tb_console_init(void);
 
@@ -78,12 +80,56 @@ void tashaboot_main(uintptr_t fw_arg)
 	}
 #endif
 
+	{
+		/* spin table gates into the dtb, one per cpu node */
+		extern unsigned long *tb_spin_gates_ptr;
+		extern int tb_dtb_patch_spin_table(uintptr_t dtb,
+						  uintptr_t *gates,
+						  int ngates);
+		int n;
+
+		if (tb_spin_gates_ptr) {
+			extern unsigned char tb_pen_stamps[8];
+			int c;
+
+			n = tb_dtb_patch_spin_table(fw_arg,
+						    tb_spin_gates_ptr, 8);
+			dprintf(ALWAYS, "dtb: %d release addrs patched\n", n);
+
+			/* who made it to the pen */
+			for (c = 1; c < 8; c++) {
+				if (tb_pen_stamps[c])
+					break;
+			}
+			dprintf(ALWAYS, "pen: %s\n",
+				c < 8 ? "secondaries waiting" :
+					"no secondaries parked");
+		}
+	}
+
 	ret = tb_load_semihosting(TB_BOOTFILE, TB_LOAD_ADDR, &img);
 	if (ret) {
 		dprintf(ALWAYS, "load failed (%d), halting\n", ret);
 		platform_halt();
 	}
 
+	/*
+	 * the initrd rides after the kernel, the dtb /chosen carries
+	 * linux,initrd-start and -end, both already patched in place
+	 * with this layout.
+	 */
+	{
+		extern int tb_load_raw(const char *fname,
+				       uintptr_t load_addr);
+		int r = tb_load_raw(TB_INITRD_FILE, TB_INITRD_ADDR);
+
+		if (r == 0)
+			dprintf(ALWAYS, "initrd at %lx\n",
+				(unsigned long)TB_INITRD_ADDR);
+		else
+			dprintf(ALWAYS, "no initrd (%d)\n", r);
+	}
+
 	dprintf(ALWAYS, "loaded %llu bytes at %lx, entry %lx\n",
 		(unsigned long long)img.size, img.load, img.ep);
 	dprintf(ALWAYS, "jumping\n");