tashaboot: arm64 bringup, semihosting payload loader

consoles on the pl011 the dtb points at, walks the memory node and
chosen, loads an arm64 kernel Image over semihosting and jumps to it
with the documented register state. string functions, printf and
libfdt are vendored from lk (lk2nd) and u-boot so the libc surface is
the one those projects already proved. built and booted on qemu virt,
payload exits clean through semihosting.

1 files changed, 54 insertions, 0 deletions

diff --git a/include/endian.h b/include/endian.h
new file mode 100644
index 0000000..42f880c
--- /dev/null
+++ b/include/endian.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * endian.h - byte order swaps. arm64 and ppc64le are both little
+ * endian, so the macros compile to nothing there, but the big endian
+ * fallbacks stay so a BE target builds without a rewrite.
+ *
+ * Copyright (C) 2026 Bradley Morgan <brads@mainlining.org>
+ */
+
+#ifndef __ENDIAN_H
+#define __ENDIAN_H
+
+#include <stdint.h>
+
+static inline uint16_t __swap16(uint16_t x)
+{
+	return (uint16_t)((x << 8) | (x >> 8));
+}
+
+static inline uint32_t __swap32(uint32_t x)
+{
+	return ((x << 24) |
+		((x & 0xff00) << 8) |
+		((x & 0xff0000) >> 8) |
+		(x >> 24));
+}
+
+static inline uint64_t __swap64(uint64_t x)
+{
+	return ((uint64_t)__swap32((uint32_t)x) << 32) |
+	       __swap32((uint32_t)(x >> 32));
+}
+
+#if defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+
+#define le16_to_cpu(x)	__swap16(x)
+#define le32_to_cpu(x)	__swap32(x)
+#define le64_to_cpu(x)	__swap64(x)
+#define cpu_to_le16(x)	__swap16(x)
+#define cpu_to_le32(x)	__swap32(x)
+#define cpu_to_le64(x)	__swap64(x)
+
+#else
+
+#define le16_to_cpu(x)	(x)
+#define le32_to_cpu(x)	(x)
+#define le64_to_cpu(x)	(x)
+#define cpu_to_le16(x)	(x)
+#define cpu_to_le32(x)	(x)
+#define cpu_to_le64(x)	(x)
+
+#endif
+
+#endif