2 files changed, 88 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
new file mode 100644
index 0000000..342a2ff
--- /dev/null
+++ b/arch/arm64/include/asm/mmu.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MMU_H
+#define __ASM_MMU_H
+
+/*
+ * VMSAv8-64 stage 1 translation at EL2. descriptor layouts and
+ * attribute fields per the ARM ARM (DDI 0487), block and table
+ * descriptors D5-2444, page descriptors D5-2447, stage 1 attribute
+ * fields D5-2451, MAIR region attributes D5-2476.
+ */
+
+#include <stdint.h>
+
+/* descriptor bits[1:0]: 0b01 block (page at level 3), 0b11 table */
+#define TB_DESC_FAULT		0ULL
+#define TB_DESC_BLOCK		1ULL
+#define TB_DESC_TABLE		3ULL
+
+/* lower block/page attribute bits, D5-2451 */
+#define TB_DESC_AF		(1ULL << 10)	/* access flag, set by hand */
+#define TB_DESC_SH_IS		(3ULL << 8)	/* inner shareable */
+#define TB_DESC_XN		(1ULL << 54)	/* XN at EL2, no execute */
+
+/* MAIR_ELx attribute indices used by the maps below */
+#define TB_ATTR_NORMAL		0		/* writeback, read allocate */
+#define TB_ATTR_DEVICE		1		/* device nGnRE */
+
+/*
+ * TCR setup, 4KB granule. T0SZ 16 gives a 48-bit VA and the walk
+ * starts at level 0 (Address size configuration, D5-2399), which is
+ * what the three level table structure below assumes. a 39-bit VA
+ * (T0SZ 25) would start the walk at level 1 and misread the whole
+ * table.
+ */
+#define TB_TCR_T0SZ_48		16
+#define TB_TCR_SH0_IS		(3ULL << 12)
+#define TB_TCR_TG0_4K		(0ULL << 14)
+#define TB_TCR_IRGN0_WB		(1ULL << 8)
+#define TB_TCR_ORGN0_WB		(1ULL << 10)
+#define TB_TCR_IPS(x)		((uint64_t)(x) << 16)	/* PA size from PARange */
+
+/* the map itself, PA == VA everywhere, identity */
+#define TB_MAP_MMIO_BASE	0x00000000ULL
+#define TB_MAP_MMIO_SIZE	(1ULL << 30)	/* low 1GB, devices live here */
+#define TB_MAP_RAM_BASE		0x40000000ULL
+#define TB_MAP_RAM_SIZE		(128ULL << 20)	/* qemu virt default, 128MB */
+
+int tb_mmu_enable(void);
+void tb_mmu_disable(void);
+
+#endif /* __ASM_MMU_H */
diff --git a/arch/arm64/include/asm/psci.h b/arch/arm64/include/asm/psci.h
new file mode 100644
index 0000000..d7ce0f3
--- /dev/null
+++ b/arch/arm64/include/asm/psci.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_PSCI_H
+#define __ASM_PSCI_H
+
+#include <stdint.h>
+/*
+ * PSCI 0.2 handler at EL2, the Power State Coordination Interface
+ * per DEN 0022. the payload calls it through the conduit the dtb
+ * names, hvc here, the call traps to EL2 and this dispatches.
+ */
+
+/* standard function ids, DEN 0022 table 5-1 */
+#define PSCI_FN_VERSION		0x84000000
+#define PSCI_FN_CPU_OFF		0x84000002
+#define PSCI_FN_CPU_ON		0x84000003
+#define PSCI_FN_SYSTEM_OFF	0x84000008
+#define PSCI_FN_SYSTEM_RESET	0x84000009
+
+/* version 0.2, major 0 minor 2 */
+#define PSCI_VERSION_0_2	0x00000002
+
+/* error codes, DEN 0022 */
+#define PSCI_RET_SUCCESS		0
+#define PSCI_RET_NOT_SUPPORTED		-1
+#define PSCI_RET_INVALID_PARAMS		-2
+#define PSCI_RET_DENIED			-3
+#define PSCI_RET_ALREADY_ON		-4
+#define PSCI_RET_ON_PENDING		-5
+#define PSCI_RET_INTERNAL_FAIL		-6
+#define PSCI_RET_NOT_PRESENT		-7
+#define PSCI_RET_DISABLED		-8
+
+/* the asm HVC vector calls this with the caller's x0-x3 in place */
+uint64_t tb_psci_dispatch(uint64_t fn, uint64_t x1, uint64_t x2,
+			  uint64_t x3);
+
+#endif /* __ASM_PSCI_H */