1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm64/kernel/boot.S b/arch/arm64/kernel/boot.S
new file mode 100644
index 0000000..615be06
--- /dev/null
+++ b/arch/arm64/kernel/boot.S
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * boot.S - the final jump to the payload. x0 = dtb, x1 = x2 = x3 = 0,
+ * MMU and caches off, D cache flushed, I cache invalidated. that is
+ * the whole contract from Documentation/arch/arm64/booting.rst.
+ *
+ * Copyright (C) 2026 Bradley Morgan <brads@mainlining.org>
+ */
+
+#include <asm/linkage.h>
+
+.pushsection .text.tb_boot_linux, "ax"
+ENTRY(tb_boot_linux)
+	/* ep in x0, dtb in x1, per the kernel boot protocol */
+
+	/*
+	 * cache maintenance first, register setup last. x0-x18 are
+	 * caller saved per the AAPCS, the flush helpers are free to
+	 * clobber them, so the args ride in x20/x21 across the calls.
+	 */
+	mov	x20, x0		/* entry point */
+	mov	x21, x1		/* dtb */
+
+	bl	tb_flush_dcache_all
+	bl	tb_invalidate_icache_all
+
+	mov	x8, x20
+	mov	x0, x21
+	mov	x1, xzr
+	mov	x2, xzr
+	mov	x3, xzr
+
+	/* MMU off, caches off, the kernel sets up its own state */
+	mrs	x9, sctlr_el1
+	bic	x9, x9, #(1 << 0)	/* M, MMU */
+	bic	x9, x9, #(1 << 2)	/* C, D-cache */
+	bic	x9, x9, #(1 << 12)	/* I, I-cache */
+	msr	sctlr_el1, x9
+	isb
+
+	br	x8
+ENDPROC(tb_boot_linux)
+.popsection